Typical L1 and L2 access latency for SoCs made from ARM Cortex-A9

Question

I am looking for L1 access latency and L2 access latency for SoC made from ARM Cortex-A9 processors such as Nvidia Tegra 2 and Tegra 3, which have multiple ARM A9 processors.

I could find some information about the L1 and L2 sizes of these architectures, but I could not get much information about the access latencies L1 and L2. The only reliable information I found is that "L2 cache timeout on Tegra 3 is 2 cycles faster than 2, while the latency in the L1 cache has not changed."

It is mentioned here that L2 on Tegra 2 has a latency of 25 cycles and it is indicated here that L1 has a delay of 4 cycles, and L2 has a latency of 31 to 55 cycles. None of these links are completely reliable. I was hoping to find more information on the Nvidia, TI, and Qualcomm websites and technical documents, but I didn’t.

EDIT: Information on similar SoCs such as OMAP4460 and OMAP4470 will also be great.

Answer 1

For an authoritative answer, you can try running lmbench ( HowTo ?) At the request of your choice.

The result set is available for AM37x (version of the TI OMAP3 family) here strong> for reference.

Also check out this presentation , which describes the latency and throughput of various cache configurations in the ARM Cortex A9 MP system.