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Pythonesque bit-slicing in Verilog?

In Python, I can choose even or odd bits:

>>> bits = ['a','b','c','d']; >>> bits[0::2] ['a', 'c'] >>> bits[1::2] ['b', 'd']

It would be very practical if I could do it in Verilog, so I would not have to expand the expression and do it manually. Extended (ie {a[0], a[2]} and {a[1], a[3]} ), this obviously will not work with my other parameterized set of wires.

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2 answers

This can be done using the generation block. Example:

 wire [FLOORS-1:0] RELEVANT; genvar i; generate for (i=0; i<FLOORS; i=i+1) begin assign RELEVANT[i] = FLOOR_REQUEST[i*2+FORWARD]; end endgenerate
  • FLOORS - width of the output wire (half the width of the input wire).
  • RELEVANT is the result.
  • FORWARD - even / odd selector (0 or 1).
  • FLOOR_REQUEST is the input.
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There is no mechanism in Verilog or SystemVerilog to execute a small snippet, such as the Python example you gave. That is, you cannot specify step 2 between bits.

You can do this with a for loop, and it doesn't need to be in the generation block, as in your own answer.

A modified example from your answer:

 always @(*) begin for (int i = 0; i < FLOORS; i++) begin RELEVANT[i] <= FLOOR_REQUEST[i*2+FORWARD]; end end

This should synthesize everything in order as long as FLOORS is a constant.

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