Method for initializing a synthesized 2D array with constant values ​​in Verilog

Question

in VHDL, I can easily do this:

constant cmdbytes : bytearray(0 to Total) := (x"05", x"00", x...}; 

I want synthesized constants, so when the FPGA starts, this array has the data that I provided. These registers are connected to VCC or ground to represent 1 or 0. Then I can use them to generate a waveform. I would also like to have a 2D byte array, which is 3D in the verilog world.

Answer 1

If you just use an array to pull one value at a time, how about using a case ? Of course, this is a long way to do this, but you can always write a script to write RTL for you.

 reg [7:0] value; reg [7:0] i; always @(posedge clk or negedge rst_n) begin if(!rst_n) i <= 8'd0; else i <= i + 1; end always @(*) begin case(i) 8'h00: value = 8'd0; 8'h01: value = 8'd34; ... endcase endcase 

Another way is to use the initial operator. As far as I know, FPGA synthesis tools allow you to set initial values ​​for arrays as follows. Again, a script to write this might be the way to go.

 reg [0:35][7:0] my_array; initial begin my_array[0] = 8'd45; my_array[1] = 8'd26; ... end 

And if your FGPA synthesis tools support some SystemVerilog, you can initialize the array as follows:

 reg [0:34][7:0] my_array = '{ 8'd90, 8'd34, ... }; // note the '{ 

Answer 2

Verilog 2005 does not allow array initialization. Although your FPGA vendor should have a tool for creating ROMs.

Answer 3

It works?

 reg [31:0] array2d[3:0] .... array2d[3:0] = {{32'd0}}; 

or

 array2d[3:0] = {32'd0, 32'd0, 32'd0, 32'd0}