Geek Answers Handbook

How to make 2-padding a number without using an adder

In a two-complement to invert the sign of a number, you usually simply negate each bit and add 1. For example:

011 (3) 100 + 1 = 101 (-3)

In VHDL there is:

 a <= std_logic_vector(unsigned(not(a)) + 1);

Thus, the synthesizer uses an N-bit adder.

Is there an even more efficient solution without using an adder?

+4
source share
2 answers

I would suggest that there is no simpler way to do this, but the adder is probably not as bad as you think.

If you are trying to invert a 32-bit number, the synthesis tool may begin with a 32-bit adder structure. However, seeing that input B always attached to 1, it can “hollow out” most of the structure due to unused gates (AND logic with one pin tied to ground, OR with one pin tied to logic 1, etc.) .

So, what would you leave with you, I would suggest that this will be a fairly efficient block of logic that simply increases the amount of input data.

+5
source

If you are just trying to create a binary bit with two additions, then unary - also works.

 a = 3'b001 ; // 1 b = -a ; //3'b111 -1 c = ~a + 1 ; //3'b111 -1

Tim also correctly pointed out that just because you use + or imply one through unary, synthesis tools can optimize this.

The full adder has 3 inputs (A, B, Carry_in) and 2 outputs (Sum Carry_out). Since for our use the second input is only 1 bit wide, and there is no carry in LSB, we do not need a “full adder”.

An absolute combiner that has 2 inputs (A, B) and 2 outputs (Sum Carry) is perfect.

For the low order, the inputs with half adders B will be high, +1 . The remaining inputs of bit B will be used to propagate Carry from the previous bit.

I don’t know how to write in verilog that you want to get half the sum, but for any size number plus 1 bit only a half adder is required, not a full one.

+1
source

More articles:


All Articles