This is a super far-fetched guess, but this code seems a little suspicious, from the pl011_startup() function to PL011 the serial port driver :
It seems that it scrolls the TX line when the port starts, which explains the pulse that you see. Of course, an additional investigation will be required before completing this, which is happening, of course.
So, I think my "answer" comes down to: does this sound weird, maybe this is something with the driver?
Of course, one way around this is to take some care at the end of the FPGA, suggesting that you have more control over it. A βcorrectβ frame will take care of this and make it clear that a false send may be discarded.
UPDATE I meant that if the "correct" messages should always be framed by a certain sequence of bytes, the FPGA can in any case reject invalid ("unpainted") data and thus become immune to a random impulse. For example, messages can be defined to always start with the characters SOH (beginning of the header) or SOT (beginning of the text) ( bytes with values ββ0x01 and 0x02 , respectively).
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