What does it mean when my processor does not support uneven memory access?

Question

I just discovered that the ARM I'm writing code on (Cortex M0) does not support equidistant memory access.

Now in my code I use a lot of packed structures, and I never had any warnings or hard errors, since Cortex can access these structures if it does not allow for uneven access?

Answer 1

Compilers like gcc understand alignment and issue the right instructions to get around alignment problems. If you have a packed structure, you should tell the compiler so that he knows in advance how to perform alignment.

Let's say you use a 32-bit architecture, but the struct packed as follows:

 struct foo __attribute__((packed)) { unsigned char bar; int baz; } 

When baz is accessed, it will load memory at the 32-bit boundary and shift all bits to position.

In this case, it will probably have a 32-bit load on the address bar and a 32-bit load on the address bar + 4. Then it will apply a sequence of logical operations, such as shift and logical and / or finally get the correct baz value of 32 -bit register.

Look at the assembly to see how it works. You will notice that unadjusted calls will be less efficient than consistent calls on these architectures.

Answer 2

Many older 8-bit microprocessors had instructions for loading (and storing) registers that were larger than the width of the memory bus. Such an operation will be performed by loading half the register from one address and the other half from the next higher address. Even on systems where the memory bus is wider than 8 bits wide (say 16 bits), it is often useful to consider memory as an address byte collection. Downloading a byte from any address will cause the processor to read half the 16-bit memory cell and ignore the other half. Reading a 16-bit value from an even address will cause the processor to read the entire 16-bit memory cell and use all this; the value will be the same as if one had read two consecutive byte addresses and combined the result, but it would be read in one operation, and not in two.

On some such systems, if you try to read a 16-bit value from an odd address, the processor will read two consecutive addresses using half of one value and the other half of another value, as if it were doing two single-byte reads and combined results. This is called unacceptable memory access. On other systems, such an operation will result in a bus error, which usually causes some form of interruption, which may or may not do something useful. The hardware to support unrelated accesses is quite complicated, and developing code to avoid unrelated accesses is usually not too complicated. Thus, such equipment usually exists only on processors that are already very complex, or on processors that will run code that was designed for processors that collect multibyte registers from single-byte reads (for example, on 8088, every 16 bits of read took two 8-bit memory samples, and a lot of 8088 code was run on subsequent Intel processors).