Relationship between Core L2 and L3 in Core i7

Question

The Intel i7 core has Ker L1 and L2 caches, as well as a large shared L3 cache. I need to know which connection connects multiple L2 to one L3. I am a student and I need to write a rough behavioral model of the cache subsystem. Is this the crossbar? One bus? ring? The links I came across mention the structural details of the caches, but none of them mention which connection on the chip exists.

Thanks,

-neha

Answer 1

Modern i7 uses a ring. From Tom Hardware :

Earlier this year, I had the opportunity to speak with Saylesh Cottapali, Intel's senior software engineer, who explained that he saw a long bandwidth of about 300 GB / s from Xeon 7500-series LLC, which included a ring bus. In addition, Intel confirmed at IDF that each of its products under development uses a bus ring.

Your model will be very crude, but you can get more information from the publicly available information about the L3 i7 performance counters.