Purpose of SystemVerilog vs C ++: link or copy?

Question

I have primarily a background of C ++. I tracked the error in the SystemVerilog code that I was working on, and was surprised to find that, in my opinion, the copy destination of the objects was actually a reference destination. This simplified code shows what I mean:

for (int i = 0; i < max_num; ++i) { var cls_obj obj1; obj1 = obj_array[i]; some_function(obj1); // modifies the object passed in // at this point BOTH obj1 and obj_array[i] are modified. // some other code goes here } 

I expected changes only obj1 . Is it because of the var keyword? How exactly does copying versus link assignment work in SystemVerilog? I find it difficult to find information from a web search.

Answer 1

Class variables in SystemVerilog are references or descriptors. Instances are created only when the new keyword is used.

So, in your example, obj1 and obj_array[i] both refer (or point) to the same instance.

By default, function parameters in SystemVerilog are passed by value. However, class descriptors are treated as values, so any class that you pass to a function is effectively passed by reference.

There is a built-in mechanism in the language to make a shallow copy when initializing a class object.

 Packet p1; Packet p2; p1 = new; p2 = new p1; 

It makes a shallow copy. For objects, only pens are copied!

This is explained in the examples in chapter 8.11 of IEEE 1800-2009.

The var keyword has nothing to do with the behavior you see. In fact, I have not even seen or used var . According to LRM, this allows you to omit the type when declaring a variable. Your code specifies a type (cls_obj), so I don’t think its presence is doing anything.