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Watch Generation Difference

What is the difference between the following codes?

initial begin clk = 0 ; forever begin #5 clk = ~clk; end end initial begin clk = 0 ; forever begin clk = #5 ~clk; end end

I know the difference between inertial and transport delays, and I know that the clock is generated in both cases (with some phase difference between them), but I want to know how the simulator responds to the following codes. same or different? How and how many events are taken into account when calculating the value?

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The difference between two of the points of use:

#5 clk = ~clk; means "wait 5 time steps", then do clk = ~clk;

For conductors B = #5 A; means B is assigned A from 5 backward. A leads B at 5 time intervals. If B is changed to A A = #5 A;

 wire B; assign B= #5 A;

Usage for wire is covered by the IEEE 1800-2012 section 6.7 Net declarations

From the update syntax @ new2androids A = #5 B; , for registers is different from wire register. B is checked every 5 time units, and A is immediately assigned a value. That is why it works to generate testbench watches.

Regarding how the simulator responds, there may be some standard planning methods that others can comment on, but to the extent that it may depend on the simulator used.

@ new2android. The following information is provided: 1996: Understanding Verilog locks and non-blocking assignments

  • #5 A = B; Pulses with a width of less than 5 are ignored by the simulator.
  • A = #5 B; Input is checked every 5 units of time and immediately assigned a value

Notes

  • All delay applications are for simulation purposes only and are not synthesized.
  • The question and answer do not account for differences when using non-blocking delay options ( B <= #5 A; #5 B <= A; ).
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