Access to inputs and outputs in submodules from testbench

Question

My device under test (DUT) has many submodules, and I would like to test some of them.

My test device will be the top level of my project - one level higher than the DUT, and since I can only see the inputs and outputs of the modules one level down, I can only access the top level inputs and outputs of the device under test.

I would like to be able to receive signals from modules with two or more levels under the test device, ideally without having to rewrite any modules to add more outputs, so the signals I want to test are connected to the upper level.

I could rewrite the device under test, but it seems time consuming, and I feel that there should be a faster way.

Is there a way to write a test device that can access signals inside submodules without overwriting DUT?

Answer 1

If you only need to track signals inside the top-level module, you can use hierarchical path pointers to span down in the dut:

dut.read_data

SystemVerilog also offers the operator bindto do something similar.

If you need to control internal signals, you must create a separate test bench for the submodule. This is time consuming, but gives you better control and allows you to achieve 100% coverage (which can sometimes be difficult at the top level).