Makefile and using $$

Question

So, I have a Makefile in which I have the following code that I am trying to understand:

for file_exe in `find . -name "zip_exe-*"`; do \
    ./$${file_exe} -d $(UNZIP_PATH)/lib; \
done

As I understand it, this piece of code will try to find the executable zip and extract these zip files in the location. But what puzzles me is how it works $${file_exe}. Why do you need a double $$? I assume that this is due to the fact that some bash commands are run from a makefile, but I can’t explain to myself why I need it $$, and a simple one $doesn’t work, because this command still works under a shell.

Answer 1

, $ make-, ${FOOBAR} $, . make specification ( ) , $$, $ . ,

for file_exe in `find . -name "zip_exe-*"`; do \
   ./${file_exe} -d some/unzip/path/lib; \
done

.

. , , , ARG_MAX.

find . -name "zip_exe-*" | \
while read -r file_exe; do \
   ./${file_exe} -d some/unzip/path/lib; \
done