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Declaring an array inside an object in VHDL

I am trying to make a buffer to store 16, 16-bit instructions for a small processor design.

I need a way to load instructions into a buffer from my testbench. So I wanted to use the std_logic_vectors array for this. However, I get a syntax error, and I'm not sure why (or if I am allowed to do this in VHDL, for that matter).

The syntax error is on the line where I declare instructions

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;




entity instruction_buffer is
    port
    (
    reset               : in std_logic;
    instructions        : in array(0 to 15) of std_logic_vector(15 downto 0);
    instruction_address : in  std_logic_vector(3 downto  0);
    clk                 : in std_logic;
    instruction_out     : out std_logic_vector(15 downto 0)
    );
end instruction_buffer;

I also tried to do this, but then I get syntax errors in the mapping of entity ports, saying that it std_logic_vectoris an unknown type. I swear VHDL syntax errors are less significant than C haha

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

package instructionBuffer is
    type instructionBuffer is array(0 to 15) of std_logic_vector (15 downto 0);
end package instructionBuffer;

entity instruction_buffer is
    port
    (
    instruction_address : in  std_logic_vector(3 downto  0);
    clk                 : in std_logic;
    instruction_out     : out std_logic_vector(15 downto 0)
    );
end instruction_buffer;
+4
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:

:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

package instruction_buffer_type is
    type instructionBuffer is array(0 to 15) of std_logic_vector (15 downto 0);
end package instruction_buffer_type;

:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

use work.instruction_buffer_type.all;

entity instruction_buffer is
    port
    (
    instruction_address : in  std_logic_vector(3 downto  0);
    instructions        : in instructionBuffer;
    clk                 : in std_logic;
    instruction_out     : out std_logic_vector(15 downto 0)
    );
end instruction_buffer;

, . .

+5

, . generics :

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

package instruction_buffer_type is
constant INSTRUCTION_BUFFER_ADDRESS : integer := 4;  --bits wide
constant INSTRUCTION_BUFFER_DATA    : integer := 16; --bits wide
type instructionBuffer is array(0 to 2**INSTRUCTION_BUFFER_ADDRESS -1) of std_logic_vector (INSTRUCTION_BUFFER_DATA -1 downto 0);
end package instruction_buffer_type;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

use work.instruction_buffer_type.all;

entity instruction_buffer is
    port
    (
    instruction_address : in  std_logic_vector(INSTRUCTION_BUFFER_ADDRESS-1 downto  0);
    instructions        : in instructionBuffer;
    clk                 : in std_logic;
    instruction_out     : out std_logic_vector(INSTRUCTION_BUFFER_DATA-1 downto 0)
    );
end instruction_buffer;
+5

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