The stp aarch64 command should be used with an "non-contiguous pair of registers",

Question

The aarch64 architecture has no instructions for multiple storage and loading, i.e. there are no equivalents of stm and ldm from the armv7 arch. Instead, you should use the stp and ldp commands to store and load pairs of registers.

Enabling the ARM reference guide:

http://www.element14.com/community/servlet/JiveServlet/previewBody/41836-102-1-229511/ARM.Reference_Manual.pdf

There are no commands with multiple registers LDM, STM, PUSH and POP, but it is possible to load an intransitive pair of registers.

My question is: what does non-contiguous mean or refers here? My instant reaction was that it means that you cannot use sequentially numbered registers with these commands, for example.

stp x0, x1, [sp, #-16]!

is illegal. However, I do not believe that this is so. I saw an example of code that does just that, and besides, I managed to get (Apple) Clang to create similar code, for example.

stp x1, x0, [fp, #-16]!

For life, I cannot think what adjoins then. I thought this could be due to the use of overlapping registers, for example.

stp x0, x0, [sp, #-16]!
stp w0, x0, [sp, #-12]!

However, I saw an example of code doing such things (not to say that the code was right!). In addition, I would explicitly use terminology that overlaps, rather than adjacent, if that were the case.

Any ideas?

Answer 1

A32 (ARM) LDRD/STRD *, , , ..

LDRD r0, r1, [sp]   @ OK
LDRD r0, r7, [sp]   @ <Rt> and <Rt2> are non-contiguous: invalid
LDRD r3, r4, [sp]   @ Contiguous but <Rt> odd-numbered: invalid

[ , , .]

, A64 LDP/STP , , , - , .

, ARMv8 ARM, , .

_{* T32 (Thumb) , , , A64.}