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Why does the AAPCS Standard Procedure Call Standard for ARM Architecture require the SP to be 8-byte aligned?

Since this is a recurring topic, I ask a question about this.

According to AAPCS :

5.2.1.1 Universal stack constraints

     
  •   
  • SP mod 4 = 0. The stack should always be bound to the word boundary  
     

5.2.1.2 Stack restrictions in the open interface

     
  •   
  • SP mod 8 = 0. The stack must be combined with a double word.  

What is rational 8-byte alignment?

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3 answers

There are many possible reasons:

  • Tools require it.
  • ldrd/strd required for some architectures.
  • Many ARM buses are 64 bits wide. 8byte alignment will result in faster memory access.
  • 64 (128B, 1024b).
  • TLB 64 (1k 4k +).
  • Tagged pointers (++, ..). 8- .

, , . , . 1 , . . 5, .

, , - , , , - . , , , , .

, ARMv7/A. , 0 Cortex M3 (CM3_r0) SP 8 .

ABI ARM® Architecture Advisory Note - SP 8 AAPCS -

0

ldrd strd.

.

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, STRD LDRD 8- . , , 8-, .

ARM:

, LDRD STRD, ARM v5TE . , LDRD STRD .

ARM ABI Advisory Note.

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