Using objects from another file in VHDL

Question

How to "include" another file from the workspace in VHDL, and then use the entity architecture that is implemented in another file? Here is what I have, but it’s wrong:

updated code:

library ieee;
use ieee.std_logic_1164.all;
library Part2;
use Part2.all;


entity problem4Gates is
    port(X,Clk: in std_logic; Q: out std_logic_vector(2 downto 0)) ;
end entity problem4Gates;  

architecture behavioral OF problem4Gates IS  

for all: yourGateName use entity  Part2.JKflipFlop(jkFF); --port (J, K, Clk, Preset, Clear : in std_logic; Q, Qn : Buffer std_logic) --JKflipFlop --jkFF    
signal s0, ns0, s1, ns1, s2, na2, ps0, ps1, ps2, restart : std_logic :='0';
begin
    process(clk)
    begin                  
         yourgatename( ns0, clk, '0', restart, Q(0), ns0 );
    end process;
end architecture behavioral;

Now I get 2 errors:

# Error: COMP96_0078: Part3.vhd : (13, 10): Unknown identifier "yourGateName".
# Error: COMP96_0134: Part3.vhd : (13, 10): Cannot find component declaration.

Answer 1

How to "include" another file from the workspace in VHDL, and then use the entity architecture that is implemented in another file?

You do not include the file. VHDL is not C.

If you compile several different architectures of a particular object, they can all be in the same file, even in the same file as the object, or they can be scattered across several files.

- - . :

inst_of_one_arch     : entity work.some_entity(one_arch) port map....
inst_of_another_arch : entity work.some_entity(another_arch) port map....

, .