Common UVM Variables

Question

I have doubts about UVM. Think that I have a DUT with two interfaces, each with its own agent, generating transactions with the same clock. These transactions are processed by analyzing the import (and recording functions) on the scoreboard. My problem is that both of these transactions read / change the common variables of the scoreboard.

My questions:

1) Should I guarantee mutual exclusion explicitly, although a semaphore? (Yes I guess)

2) Is this, in general, the right way?

3) and the main problem, can somehow fix the execution order?

Depending on this order, the values ​​of common variables can change, causing inconsistency. Moreover, this order is fixed by specifications.

Thanks in advance.

Answer 1

Although the tasks and functions of SystemVerilog are performed simultaneously, they do not run in parallel. It is important to understand the difference between parallelism and concurrency, and this has been explained well here .

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Answer 2

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Answer 3

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Answer 4

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