UVM Block Race Conditions

Question

I have doubts about race conditions in SystemVerilog, especially in UVM. In the standard case, we have several drivers that control our spirit in the same front of the watch, generating some function calls on the display. These calls are simultaneous, and it is realistic that they check / modify some common variables in the gold reference model. If these operations are performed with non-blocking assignment, there will be no problems, but with the purpose of blocking there may be race conditions. What is the best way to overcome this problem? To implement the gold reference model is not in the classroom? thanks in advance

An example of a pseudo-code of a scoreboard may be:

function void write_A(input TrA A);
    if(GRF.b >= 100 && A.a==1)
        GRF.c = 1;
endfunction

function void write_B(input TrB B);
    GRF.b+=B.b;
endfunction

Of course, the result depends on the execution order of these two functions, which is unknown. It can be solved using some synchronization mechanism, but things get more complicated when many people write parallel functions. Using non-blocking assignments will make the situation more clear and simple ... maybe the solution could be to have all GRF members static?

Answer 1

The problem is that you are trying to simulate the behavior of RTL using behavioral code. You use several functions in several threads and call them all on the same clock front in random order. There is no solution to this problem, except to complete the order when performing your operations.

- @(posedge clk) . .

,

@(posedge clk)
  write_A(A);

@(posedge clk)
  write_B(B);

@(posedge clk) begin
  write_A(A);
  write_B(B);
end

.

Answer 2

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Now, in the system verilogue, many other areas have been added, such as the obstacle area, the observed area, the deferral area.