Can I use the clock frequencies of a Vivado block in my VHDL?

Question

I am building a design in Vivado, and I am wondering if I can use the clock frequencies of the block diagram in my HDL.

I want to take FREQ_HZ, which the flowchart knows about and distributes as part of the DRC, and passes it to my own IP blocks (using a shared VHDL file). This is so that I can do things like adjust internal calculations to generate delays in microseconds, bit rates, etc.

I could do this with a manual setting, but this will require manual maintenance and will be error prone.

Answer 1

, TCL . TCL script, FREQ_HZ .