Fill 0 with 1 between two 1 (synthesized)

Question

Suppose that MSB_limitand LSB_limit. These two act like two flags and all the bits between them (even 1 - I think this simplifies the problem) should go to 1 .

Is there a synthesized solution for this?

Example problem:

MSB_limit = 7;
LSB_limit = 2;

//Let suppose our register is 16bits, desired output:

 0000000011111100
 ^       ^    ^ ^
 |       |    | |
15       7    2 0       //positions

Answer 1

unsigned int my_reg = 1<<(MSB_limit-LSB_limit+1);  // 0000000001000000
my_reg --; // 0000000000111111
my_reg <<= LSB_limit; // 0000000011111100

Answer 2

Easily reachable with for-loops:

SystemVerilog (IEEE 1800):

logic [N-1:0] my_reg;
always_comb begin
  foreach(my_reg[idx])
     my_reg[idx] = idx inside {[LSB_limit:MSB_limit]};
end

Verilog (IEEE 1364-2001 or higher):

reg [N-1:0] my_reg;
integer idx;
always @* begin
  for (idx = 0; idx < N; idx=idx+1) begin
    my_reg[idx] = (idx >= LSB_limit) && ( idx <= MSB_limit);
  end
end

Answer 3

What about a replication statement?

assign out = { '0, { MSB_limit-LSB_limit+1{1'b1} }, { LSB_limit{1'b0} } };