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Calling the Makefile of the Parent Directory

I have a project with the following directory structure:

foo/
foo/Makefile
foo/bar/

My goal is to add a file foo/bar/Makefile, so if I call makein foo/bar, the parent directory's Makefile will be used. This is a kind of inverted recursive Makefile structure (I want each Makefile to call the parent directory until it reaches the project root).

Symlinking error, because a call from the wrong directory interrupts all relative paths:

$ ln -s ../Makefile foo/bar/Makefile
$ make -C foo/bar
[error]

The only solution I found was to write a Makefile that captures all the targets that interest me and calls the parent directory for this purpose:

$ cat foo/bar/Makefile
all clean:
    $(MAKE) -C .. $@

It is laborious and easy to break. Is there a more elegant solution?

Justification

LaTeX, .tex , .. make .

+4
3

, " ". Makefile Makefile:

all:
    @make -C .. $@
%:
    @make -C .. $@

, all match-everything, make : make: *** No targets. Stop. make: *** No targets. Stop.

+3

make :

make-foo() {
    make -C /absolute/path/to/foo "$@"
}
+2

Makefile Make . Make , .

GNU Make . ( , ) Make script, , Make ( , ). " " .

script , Makefile, , cd - . , , Make .

In my practice, I also used the more complex version above, where the script wrapper examines the given arguments, and for those that are targets, adds them to the path to the subdirectory from which it started. So that

subdir>make foobar

equivalently

>make subdir/foobar
+1
source

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