I'm just trying to develop a more sophisticated Z80 CP / M system with a lot of peripherals. While reading the documentation, I came across the (undocumented?) Z80 processor behavior when accepting an interrupt in IM0.
When an interrupt occurs, the Z80 activates M1 and IORQ to signal to an external device: "Hey, give me the operation code." All is well if the opcode is first 00 or something like that. Now the documentation says that any code can be passed to the processor, for example, CALL.
But now comes the undocumented part: "The first byte of a multibyte instruction is read during the interrupt acknowledgment cycle. Subsequent bytes are read using a normal memory read sequence."
A "normal reading sequence in memory." How can I determine if the CPU wants to get a byte from memory, or instead the next byte from the device?
EDIT: I think I found a (good?) Solution: I can determine the start of the interrupt confirmation loop by analyzing IORQ and M1. I can also detect the following “regular” opcode sample by analyzing MREQ and M1. This way I can set the trigger triggered by these two AND signals, i.e. The trigger is 1 while the processor is reading data from the io device. I can use this to ban bus drivers to and from memory.
My intentions? I am developing an interrupt controller with 8 priority inputs in CPLD. It logs a 16-bit address for each interrupt. Just for fun :-)