, , , OP.
( 2) , 4 :
2^3 2^2 2^1 2^0 (Base 2)
8 4 2 1
, . 4 hex :
16^3 16^2 16^1 16^0
4096 256 16 1
2, , , MSB ( ) .
-2^3 2^2 2^1 2^0 (Base 2, Twos complement)
-8 4 2 1
, . 4 4 .
Base 2: Twos complement 4 integer, 4 bit frational
-2^3 2^2 2^1 2^0 . 2^-1 2^-2 2^-3 2^-4
-8 4 2 1 . 0.5 0.25 0.125 0.0625
, Verilog , . . verilog, reg logic, . verilog _ , . .
2.5 8'b0010_1000, 16 , 16 _, .
A B, A * B :
Integer bits = A.integer_bits + B.integer_bits.
Fractional bits = A.fractional_bits + B.fractional_bits.
[4 Int, 4 Frac] * [4 Int, 4 Frac] = > [8 Int, 8 Frac]
reg [7:0] a = 0010_1000;
reg [7:0] b = 0010_1000;
reg [15:0] sum;
always @* begin
sum = a * b ;
$displayb(sum);
$display(sum);
end
EDA.
. 16 Int 16 . , , .
Q & A, 22 .