I am wondering what is the optimal order for a sequence of instructions like the ones below for Intel processors between Core 2 and Westmere. This is the AT & T syntax, so commands pxorare reads in memory, and movdqawrite to memory:
movdqa %xmm0, -128+64(%rbx)
movdqa %xmm1, -128+80(%rbx)
movdqa %xmm2, -128+96(%rbx)
movdqa %xmm3, -128+112(%rbx)
pxor -128(%rsp), %xmm0
pxor -112(%rsp), %xmm1
pxor -96(%rsp), %xmm2
pxor -80(%rsp), %xmm3
movdqa %xmm8, 64(%rbx)
movdqa %xmm9, 80(%rbx)
movdqa %xmm10, 96(%rbx)
movdqa %xmm11, 112(%rbx)
pxor -128(%r14), %xmm8
pxor -112(%r14), %xmm9
pxor -96(%r14), %xmm10
pxor -80(%r14), %xmm11
movdqa %xmm12, 64(%rdx)
movdqa %xmm13, 80(%rdx)
movdqa %xmm14, 96(%rdx)
movdqa %xmm15, 112(%rdx)
pxor 0(%r14), %xmm12
pxor 16(%r14), %xmm13
pxor 32(%r14), %xmm14
pxor 48(%r14), %xmm15
%r14, %rsp, %rdxAnd %rbxare different multiples of 256. In other words, in the above instructions do not have non-obvious pseudonyms, and were derived data for consistent access to large blocks of data. All available memory lines are in L1 cache.
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movdqa %xmm0, -128+64(%rbx)
movdqa %xmm1, -128+80(%rbx)
pxor -128(%rsp), %xmm0
movdqa %xmm2, -128+96(%rbx)
pxor -112(%rsp), %xmm1
movdqa %xmm3, -128+112(%rbx)
pxor -96(%rsp), %xmm2
movdqa %xmm8, 64(%rbx)
pxor -80(%rsp), %xmm3
movdqa %xmm9, 80(%rbx)
pxor -128(%r14), %xmm8
movdqa %xmm10, 96(%rbx)
pxor -112(%r14), %xmm9
movdqa %xmm11, 112(%rbx)
pxor -96(%r14), %xmm10
movdqa %xmm12, 64(%rdx)
pxor -80(%r14), %xmm11
movdqa %xmm13, 80(%rdx)
pxor 0(%r14), %xmm12
movdqa %xmm14, 96(%rdx)
pxor 16(%r14), %xmm13
movdqa %xmm15, 112(%rdx)
pxor 32(%r14), %xmm14
pxor 48(%r14), %xmm15
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