VHDL integer range inclusive? FPGA vs. Simulation Difference

Question

I am new to FPGA. I did some simple tests and I found a problem that I do not quite understand.

I have a 50 MHz clock source.

I have a signal defined as:

SIGNAL ledCounter : integer range 0 to 25000000 := 0;

When the ledCounter reaches 25,000,000, I switch the LED and reset the counter. This works fine directly on the FPGA.

IF (rising_edge(CLK)) THEN
    ledCounter <= ledCounter + 1;

    IF (ledCounter = 25000000) THEN
        ledCounter <= 0;
        toggle <= not toggle;
        LED(0) <= toggle;
    END IF;
END IF;

When starting inside ModelSim, I get an error when the counter reaches 25000000. To start it in the simulator, I have to define the range as:

SIGNAL ledCounter : integer range 0 to 25000001 := 0;

Does anyone have an idea why this is happening? The code works on the FPGA well, but will not work in the simulator without the above modification.

: modelsim : - . HDL. C:/Users/robert/Documents/fpga/testsim/test.vhd 20 __17

Answer 1

- , lineCounter <= ledCounter + 1 . ledCounter 25000001, , , . , else:

IF (rising_edge(CLK)) THEN
    IF (ledCounter = 25000000) THEN
        ledCounter <= 0;
        toggle <= not toggle;
        LED(0) <= toggle;
    ELSE
        ledCounter <= ledCounter + 1;
    END IF;
END IF;

, ledCounter 25000001 . , .