Select interface parameters in module declaration

Question

Say I have a parameterized interface like

interface Foo;
    parameter WIDTH=8;
    logic [WIDTH-1:0]data;
endinterface

Now I would like to use one of these interfaces with a width (say) of 16 in the module. How can i do this? I tried

module foo(Foo #(.WIDTH(16)) in, output logic [15:0]out);
    assign out=in.data;
endmodule

but get the error:

Error (10170): Verilog HDL syntax error at test.sv(6) near text "#";  expecting ")"

Answer 1

The current SystemVerilog BNF syntax does not specify an interface interface parameter specification. It will get parameterization from the instance that connects to the port

module foo(Foo in, output logic [in.WIDTH-1:0] out);
   assign out = in.data;
endmodule          

interface Foo #(
    parameter WIDTH=8
          );
    logic [WIDTH-1:0]data;
endinterface : Foo

module top;
   Foo#(.WIDTH(16)) f();
   logic [15:0] o;
   foo dut(f,o);
endmodule : top

You can put a development check for a specific parameterization, which will lead to a compilation error if the check fails

module foo(Foo in, output logic [in.WIDTH-1:0] out);
   if (in.WIDTH != 16) $error("Width not 16");

   assign out = in.data;
endmodule          

The above statement is ifnot a procedural expression, it is a blockgenerate-if