My question is: How can a memory barrier force me to streamline work on other processors?
What does the love of robert mean? Why is this required? What is this order he could talk about? Does he talk about planning queues here?
If so, does each processor in the SMP have a different scheduling queue? I'm confused
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1: CPU1: task->state = someModifiedStuff 2: CPU1: changed = 1; 3: CPU2: if (changed) 4: CPU2: ...
, 1 2. . SMP 1 2, 3 , . , CPU1 2 ( 1), CPU2 3 4, CPU2 , , , CPU1, .
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- volatile ( ++ ). , (, lock) volatile, - fence ( : . 7.5.5 http://www.intel.com/content/www/us/en/architecture-and-technology/64-ia-32-architectures-optimization-manual.html)
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lock
fence
, ?
x = 0; thread 1: thread 2: a.lock(); a.lock(); x++; x++; a.unlock(); a.unlock();
x 2. , . , (a x , , lock() ):
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lock()
x = 0; thread 1: thread 2: x++; x++; a.lock(); a.lock(); a.unlock(); a.unlock();
x 2 1.
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