Unnecessary spaces in Verilog Display

Question

I am trying to display 32 bit values ​​in decimal format, and this works fine except for the weird amount of unnecessary spaces between my% b and the previous character.

for example: if I have a 32-bit register a with a decimal value of 33, I will use something like this

initial
begin
    $display("a=%d;", a);
end

the output in cmd will look something like this: a = ___________________ 33;

The line simply represents the long empty space between% b and the previous char. Can someone explain to me why this is happening? And how can I get rid of them?

Answer 1

In IEEE Std 1800-2012 (21.2.1.3) you can find the following information:

. .

33. , , :

$display("a=%0d;", a);

0 % d (, ), . .