Creating a pipelined processor with instructions issued in alternating clock cycles

Question

Why can't we design a (semi) pipelined processor that issues an instruction on each alternate clock cycle, rather than a pipelined processor that issues an instruction on every alternate clock cycle? Waiting for teams is likely to reduce the dangers and kiosks that we are trying to solve in a difficult way. This can completely eliminate branches and thus save expensive piping.

Answer 1

You answered your question in the comments. You can design one, but you are essentially sacrificing potential performance to simplify your design. A small deviation from what you offer is called a barrel processor . Each cycle, the processor takes one command from another thread, and this simplifies the pipeline. HEP architecture is another variation of this idea.