What cache coherence protocol does Intel and AMD use?

Question

For my undergraduate, I must analyze the effectiveness of False Sharing on multi-core systems. Therefore, looking at the different types of cache coherence protocols that I found on Wikipedia, Intel has developed the MESIF cache matching protocol, but there is no information that Intel also uses.

Looking at the guide Intel® 64 and IA-32 Developer's Guide: Vol. 3A I could not find anything about MESIF, but the MESI protocol. So the question is whether Intel is using its own caching protocol. Or am I looking for it in the wrong document.

Answer 1

Intel uses the MESIF protocol ( http://www.realworldtech.com/common-system-interface/5/ , https://en.wikipedia.org/wiki/MESIF_protocol ) in QuickPath, and AMD uses the MOESI protocol ( https: / /en.wikipedia.org/wiki/MOESI_protocol , http://www.m5sim.org/MOESI_hammer ) with or without a probe filter in HyperTransport. But these protocols are designed for interchip communication (the AMD Bulldozer connector has 2 chips in the MCM). As far as I know, in both processors in-circuit coherence is done in the L3 cache.

A tool you can use to check for NUMA performance issues is numagrind: http://dx.doi.org/10.1109/IPDPS.2011.100