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What is needed to install on a new device?

In terms of high level, what is required to install a new device using Yosys? I would like to target the Xilinx XC9572XL. I have one of these development boards: XC9572XL-CPLD-development-board-v1b . The architecture of this CPLD is pretty well covered in the Xilinx documentation here .

I think I need to do the following:

  • Find out how to get Yosys to synthesize a project into a list of compounds based on the sum of the product and the D-type Flip Flop.
  • List this netlist as a BLIF format from Yosys.
  • Create a locksmith (similar to arachne-pnr for ICE40 FPGA) for XC9572XL
  • Output the JEDEC file with the corresponding fuses that must be installed to implement the design in the previous step.
  • Flash design for CPLD using xc3sprog.

Looks like. The hard bit creates the locksmith tool. This tool needs to understand CPLD resources, and then needs some smart algorithms to match the design and output the necessary fuses in JEDEC format. One of the missing parts is the mapping between the “fuses” in the physical CPLD and the fuses in the JEDEC file. It should be reverse engineering. I note that the Xilinx WebPACK ISE JEDEC file contains 46,656 fuses. Each of them will return to some custom node in CPLD.

I would like to know what others think of this approach. What types of problems can I encounter?

, ? Xilinx , , JEDEC , ?

XC9572XL ...

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2
  • , Yosys , D- Flip Flop.
  • BLIF Yosys.

ABC BLIF . :

$ yosys -p synth -o test.blif tests/simple/fiedler-cooley.v
$ yosys-abc
abc> read_blif test.blif
abc> collapse
abc> write_pla test.pla

, .pla( , yosys, ) JEDEC.

, ?

IANAL. TINLA.

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CoolRunner-II? RE (https://recon.cx/2015/slides/recon2015-18-andrew-zonenberg-From-Silicon-to-Compiler.pdf) . Yosys , .

, ( AND/OR pterms, OR-).

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EDIT: , (17 USC 906), . ISE , , , ; .

, XC9500XL - 350 ( , , ), EEPROM/flash- . CoolRunner-II - 180 4 5 , .

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