Testing VHDL / FPGA using Python and a simulator

Question

The standard way to test code logic VHDLis to write a test bench in VHDL and use a simulator, for example ModelSim; which I have done many times.

I heard that instead of writing test benches in VHDL, engineers now use Python to test VHDL code there.

Questions:

• How it's done?

  • Is this done by writing a test bench in Python and then compiling this Python file or by contacting Modelsim?
  • Is this done in Python using the myHDL module and then linking / importing your VHDL file to Python? So how is the timing chart generated?

• When writing a test bench in Python, can you use standard Python coding / modules or just a module like myHDL?

  • For example, if I want to test the TCP / IP stack in VHDL, can I use the socket module in Python for this (i.e. import the socket)?

• Is there a link, document or tutorial that shows how to do this? I checked the Xilinx, Altera, and Modelsim sites, but found nothing.

The only thing I can find on the Internet about using Python for FPGA is a few packages: with myHDL, which is most mentioned.

Answer 1

Why is Python good for this?

Python - . Python, VHDL.

Python, , - . VHDL > 64 , . , . Python Decimal - .

?

, .

Python . VHDL, . .

VHDL testbench, , Python. , , Linux mkfifo, , , Python .

Python

, , . , TCP/IP , , , .

, , 1155120: https://electronics.stackexchange.com/questions/106784/can-you-interface-a-modelsim-testbench-with-an-external-stimuli

Answer 2

, - , SystemC/myHdl/HWToolkit, .

HDL python, , cocotb/PyCoRAM . .

, , + / , . / . python-hw HWToolkit : tx_rx_test.py

Answer 3

IO python File-IO VHDL .

, , . Systemverilog Superset Modelsim, "Questa Prime" ( ), .

, python / , . - - . . VPI/VLI/FLI/PLI/DPI ( , / ), . .. , , sim, ..

Systemverilog (IEEE-1800) IC IC . .so , testbench ( , ), SV , UCDB.

Modelsim . : https://verificationacademy.com/, SV-... , VHDL , , SV, - .

Answer 4

PyVHDL. Python VHDL Eclipse GUI , VCD.

GUI: https://i.stack.imgur.com/BvQWN.jpg