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Permanent VHDL in Generics

entity blabla is
generic(
       register_width : integer := 32;
       --Assuming register_width > 4
       constant AVAILABLE_FOR_USER : integer := register_width - 4 --allowed in 2008     
       );
port   (
           clk : in std_logic;  
           rst : in std_logic;
           reg : out std_logic_vector(AVAILABLE_FOR_USER-1 downto 0) 
        );
end blabla;

What would be the reason for using a constant in a common block if an instance can simply override it?

Is there a way to create a constant based on a generic type that cannot be overridden during instance creation?

or my example above, I can just substitute the calculation every time I want to use a constant, but it does not seem elegant, and if my state changes, it can cause a lot of errors and possible errors, which it increases

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I can’t answer why this is so, but probably the result of the evolution of the language.

- - PRIVATE_... ; , , , , .

, , ; :

architecture syn of blabla is
begin
 assert register_width - 4 = AVAILABLE_FOR_USER;
end architecture;
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:

library IEEE;
use IEEE.std_logic_1164.all;

entity blabla is
generic(
       register_width : integer := 32
       );
port   (
           clk : in std_logic;  
           rst : in std_logic;
           reg : out std_logic_vector(register_width - 5 downto 0) 
        );
end blabla;

architecture blabla of blabla is
  constant AVAILABLE_FOR_USER : integer := reg'LEFT+1;   
  signal SOME_INTERNAL_SIGNAL : std_logic_vector(AVAILABLE_FOR_USER-1 downto 0);

http://www.edaplayground.com/x/4AYF

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