I am looking to write a makefile to automate the compilation of a project I am working on, where files may or may not change in number. I also need to be able to quickly say make to compile the files as a debug build or release build (differentiated using the command line definition). After some research, I came up with rule patterns and made one. Here is the code that I still have:
ODIR = obj
CDIR = src
HDIR = inc
CC = g++
CFNO = -std=c++11 -wall -Wno-write-strings -Wno-sign-compare -lpaho-mqtt3c -pthread -O2 -I$(HDIR)
CF = $(CFNO) -o
OF = -c
NAME = tls_test
DEBUG = -DDEBUG -g
RELEASE = -DRELEASE
debug:
$(eval DR = $(DEBUG))
release:
$(eval DR = $(RELEASE))
all:
$(CC) $(CF) $(NAME) $(ODIR)/*.o
$(ODIR)/%.o: $(CDIR)/%.c
echo "$(CC) $(DR) $(OF) $(CF) $@ $<"
, , , , . make debug, release, make, . , , . , ?