I just passed the final exam, and a question arose that seemed impossible given the limitations. I would be glad to be mistaken, but as far as I checked, at least all my classmates agreed with my conclusion. Here is the question and answer (s) I gave:
A program fragment of program C is provided as follows:
c = a + b + 6;
while (c > 5) {
c = c - a;
b = b + 1;
}
Write the equivalent in the MIPS assembly using no more than 7 instructions, using only the following set of commands:
add, addi, sub, subi, slt, slti, bne
a, b and c are available through the registers $ t0, $ t1 and $ s0, respectively. You can use other registers as needed, but you cannot accept the initial value.
Here is the answer I gave as a few lines that I could:
add $s0, $t0, $t1
addi $s0, $s0, 6
loop: slti $t2, $s0, 6
bne $t2, $0, skip
sub $s0, $s0, $t0
addi $t1, $t1, 1
skip: subi $t2, $t2, 1
bne $t2, $0, loop
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, :
add $s0, $t0, $t1
addi $s0, $s0, 6
loop: sub $s0, $s0, $t0
addi $t1, $t1, 1
slti $t2, $s0, 6
subi $t2, $t2, 1
bne $t2, $0, loop
beq :
add $s0, $t0, $t1
addi $s0, $s0, 6
loop: slti $t2, $s0, 6
bne $t2, $0, skip
sub $s0, $s0, $t0
addi $t1, $t1, 1
skip: beq $t2, $0, loop
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Update
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, , Verilog, , , , MIPS. , , , @Smac89:
addi $t2, $t0, 6
add $s0, $t2, $t1
bne $t2, $t0, comp
loop: sub $s0, $s0, $t0
addi $t1, $t1, 1
comp: slti $t2, $s0, 6
subi $t2, $t2, 1
bne $t2, $0, loop
, . , , , . slt slti bne. , , , , 7 .
.