Make recompile unchanged files

Question

I have a make file for my program, but I recompiled everything every time I run it, even if I do not change anything. Every time I run make, it recompiles simHwIntf.cpp showHelp.cppandsendFromFile.cpp

This is my make file:

IDIR    = inc
LDIR    = -L/usr/lib/x86_64-linux-gnu/
SDIR    = src
ODIR    = obj
BINDIR  = bin
LDLIBS  = -luhd
OBJ     = $(patsubst %,$(ODIR)/%,$(O_FILES))

CC      = g++
CFLAGS  = -Wall -std=c++11 -I $(IDIR) #-Werror

BINARIES= main

C_FILES = simHwIntf.cpp showHelp.cpp  sendFromFile.cpp
H_FILES = simHwIntf.h
O_FILES = $(C_FILES:.cpp=.o)

all: $(BINARIES)
@echo "Make file executed"

$(BINARIES): $(O_FILES)
$(CC) $(CFLAGS) -o $(BINDIR)/$@ $(OBJ) $(LDIR) $(LDLIBS) 

fileCreator: fileCreator.o 
$(CC) $(CFLAGS) -o $(BINDIR)/$@ $(ODIR)/fileCreator.o

fileHandler: fileHandler.o
$(CC) $(CFLAGS) -o $(BINDIR)/$@ $(ODIR)/fileHandler.o

backYard: backYard.o
$(CC) $(CFLAGS) -o $(BINDIR)/$@ $(ODIR)/backYard.o

%.o: $(SDIR)/%.cpp $(IDIR)/$(H_FILES)
$(CC) $(CFLAGS) -c -o $(ODIR)/$@ $<

clean: 
-rm -rf $(ODIR)/*.o *~

distclean: clean
-rm -rf $(BINDIR)/*

Each time the output is in the shell:

g++ -Wall -std=c++11 -I inc  -c -o obj/simHwIntf.o src/simHwIntf.cpp
g++ -Wall -std=c++11 -I inc  -c -o obj/showHelp.o src/showHelp.cpp
g++ -Wall -std=c++11 -I inc  -c -o obj/sendFromFile.o src/sendFromFile.cpp
g++ -Wall -std=c++11 -I inc  -o bin/main obj/simHwIntf.o obj/showHelp.o obj/sendFromFile.o -L/usr/lib/x86_64-linux-gnu/ -luhd 
Make file executed

I already searched and read this: ( How to get the Makefile to recompile only the modified files? ), But nothing helped.

Anyone who could help me?

I have doubts about directories, maybe one or more directories are re-created every time I run make, and this makes everything inside look like new to the compiler.

thank

Answer 1

, , . %.o:

@echo [triggered by changes in $?]

VPATH %.o target. . GNU VPATH

Answer 2

%.o: $(SDIR)/%.cpp $(IDIR)/$(H_FILES)
     $(CC) $(CFLAGS) -c -o $(ODIR)/$@ $<

$(ODIR)/%.o: $(SDIR)/%.cpp $(IDIR)/$(H_FILES)
     $(CC) $(CFLAGS) -c -o $(ODIR)/$@ $<

Answer 3

.

myexec: objdir/myexec.o
    $(CC) $(CFLAGS) -o bindir/myexec objdir/myexec.o $(LDFLAGS)

Make , myexec . , myexec , . , .

BINARIES= main

BINARIES= $(BINDIR)/main

$(CC) $(CFLAGS) -o $(BINDIR)/$@ $(OBJ) $(LDIR) $(LDLIBS)

$(CC) $(CFLAGS) -o $@ $^ $(LDIR) $(LDLIBS)

.

Note that in general, it is a bad idea to use $ @ in conjunction with the path when creating the target in some rule (as in $ (BINDIR) / $ @ ), because this will never create the actual target file. Naked $ @ should be sufficient.