TL DR : Use cltqwhenever possible, as it is one byte shorter than exactly equivalent movslq %eax, %rax. This is a very minor advantage (so don’t sacrifice anything else for this to happen), but choose eaxif you want to sign it a lot.
This mainly applies to authors of compilers (compilation of indexed arrays of signed cycle counters); such things as extending the sign of a loop counter, each iteration occurs only when compilers fail to take advantage of the sign overflow, which is an undefined behavior, to avoid it. Human programmers will simply decide what is signed and what is not to save instructions.
: cltq Intel AT & T , cltq (cltq) EAX EDX: EAX (cltd), movsx/movs?t? : cltq ? ,
, 32-> 64- MOVSX ( movslq AT & T) , AMD64. Intel MOVSXD. 63/r ( , 3 , REX, 4 8-> 64 16-> 64 MOVSX). AMD ARPL, 64- .
, , x86 . 16- 8086, MOVSZ/MOVZX, CBW CWD. 386 MOVS/ZX ( CBW/CWD eax edx). AMD 64-.
REX MOVSX - 8- 16- , 64 , 32. movsbw, aka movsx r16, r/m8. IDK, , REX.W . , 16- MOVSX. , MOV, , 63/r REX ( Intel insn).
cltq ( CDQE) - cwtl ( CWDE) REX.W, 64 . , cbtw ( CBW), 8086 , MOVSX -. > 1 286, , -, mov ah, al/mov cl, 7/sar ah, cl .
, cwtl cwtd ( CWD: , ax dx: ax, , idiv).
AT & T . l d, ? Intel e , , , () RDX. CBW, , , al ax, 8086 16- , 16- dl: al. idiv r/m8 ax reg, dl: al ( ah, al)).
, x86. , sub eax,eax rax xor eax,eax. (mov eax,0 , . , , , , .),
ISA x86-64, , , MOVZX MOVSX ( 0F XX), , 8-. , movsx eax, byte [mem] , mov al, [mem]. ( Intel: , ALU uop). [u]int16_t , , movs/zx . , , , MOVZX r32/r64, r/m16. , CBW/CWDE/CDQE. CWD/CDQ/CQO idiv, .
, , (, insne SSE2 2 + ModRM 3 4 ). . x86-64 32-, . , - - , 32- 64- . , AMD AMD64. (, HyperThreading, , 32- 64-, , .)
CDQ , sar edx, eax, 31 CDQ 3 . xchg-with-eax ( 0x90 xchg eax,eax NOP) sar, shr, shl Reg ModRM . , , -- shift_count = 0, FLAGS).
( setcc r/m8 setcc r/m32 setcc r/m32. , , setcc r32/m8. ( dst ALU uop, setcc tmp32 8 ). , .)
AMD () AMD64, . ( , , , / , x86 .) / , , x86-64 .
. - x86 , NASM, , .
: MOVZX 32- 64- .