How to compile c files more efficiently with make

I am currently writing a toy OS. Since there are many c files where the gcc command does not change (except for the file name), is there a way to automatically select all the .c files in the directory and compile them and link them? Example: create a new example.c file I'm calling

make

and makefile does everything for me.

I do not want to use a script, only a make file.

OBJECTS=kasm.o kc.o objects/kb.o objects/screen.o objects/string.o objects/system.o objects/util.o objects/idt.o objects/isr.o
ARGS=-ffreestanding
CC=gcc
TARGET=image/boot/kernel.bin

$(TARGET): $(OBJECTS)
    ld -m elf_i386 -T link.ld -o $(TARGET) $(OBJECTS)

kasm.o: kernel.asm
    nasm -f elf32 kernel.asm -o kasm.o

kc.o: kernel.c
    gcc -m32 -c kernel.c -o kc.o $(ARGS)

objects/kb.o: include/kb.c include/kb.h
    gcc -m32 -c include/kb.c -o objects/kb.o $(ARGS)

objects/screen.o: include/screen.c include/screen.h
    gcc -m32 -c include/screen.c -o objects/screen.o $(ARGS)

objects/string.o: include/string.c include/string.h
    gcc -m32 -c include/string.c -o objects/string.o $(ARGS)

objects/system.o: include/system.c include/system.h
    gcc -m32 -c include/system.c -o objects/system.o $(ARGS)

objects/util.o: include/util.c include/util.h
    gcc -m32 -c include/util.c -o objects/util.o $(ARGS)

objects/idt.o: include/idt.c include/idt.h
    gcc -m32 -c include/idt.c -o objects/idt.o $(ARGS)

objects/isr.o: include/isr.c include/isr.h
    gcc -m32 -c include/isr.c -o objects/isr.o $(ARGS)

Edit: I thought this would be done using wildcards

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1 answer

The usual approach is to create a list of files *.cfrom a specific path specified using the function $(wildcard ...).

.o, $(patsubst ...).

%.o: %.c, .
.


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