Which processors support the MOVBE instruction?

Question

Sometimes GCC generates this command when compiling with -march=atom . Does every Intel Atom processor support MOVBE?

What other processors support this instruction? I can not find this information on the Intel website. Please, help.

Answer 1

These instructions were originally unique to the Intel® Atom ™ processor.

From Intel:

Intel® 11.0 Compilers allow you to target the Intel® Atom ™ processor using the / QxSSE3_ATOM or -xSSE3_ATOM compiler options. These options include generating a movbe instruction that is unique to the Intel® Atom ™ Processor.

In other microarchitectures ( http://instlatx64.atw.hu/ with uop information from https://agner.org/optimize/ ):

• Mainstream Intel: Haswell and later. Including Haswell Xeon (Ex-xxxx v3).
  Decoded as 2 or 3 mops, much like bswap + loading or saving.
• Mainstream AMD: The excavator and the Riesen Steamroller family have never been before.
  Effectively decodes up to one mop.

non-core processors:

• Outdated Intel Atom Order: All
• Intel Silvermont family breaks down Atom: that's it. Effectively decodes up to one mop.

• AMD Jaguar. Effectively decodes up to one mop.

• Intel Xeon Phi: Knight Landing (based on Silvermont) and higher. (Maybe not at the Knights' Corner.)

Answer 2

All Atom processors seem to support MOVBE; in any case, the first and least capable (Atom 230). (See, for example, http://www.linuxquestions.org/questions/linux-hardware-18/proc-cpuinfo-output-816192/ for proof.) I do not believe that any Intel processors that do not support Atom, support MOVBE; in any case, recent Core i7 processors do not look like that (see, for example, http://www.techsupportforum.com/forums/f108/i7-running-on-3-of-8-threads-522063.html and look for "movbe" to confirm).

You may find runtime support for MOVBE using CPUID.

Answer 3

Based on / proc / cpuinfo, the new Xeon E3 XXXX v3 also supports MOVBE

A source:

http://openbenchmarking.org/s/Intel%20Xeon%20E3-1230%20v3