Atomic operations: under the hood

Question

How do atomic operations under the hood work?

Are atomic operations so-called "lifeless"?

I am looking for a description of the "least common divisor" of atomic operations. What do all atomic operations have in common?

Answer 1

Atomation as a concept occurs in several places, I suspect that you are thinking about atomic operations in the code, but there are other meanings.

One fundamental property of a database transaction is Atomicity, see ACID for transaction properties.

In this case, you have a lot of skills, locks, etc., which almost certainly involves waiting when two control flows (or two processes) want to receive the same data.

When you come to the lines of code, I think you are thinking of a declaration (in some dummy language)

global int x = 7; 

in one thread

  x = 25000; print x; 

and in another

  print x; 

Can we say something about what the second stream will print? We could take 7 or 25000, we would be less happy to get a number that was a high order byte of 25,000 and a low byte of 7, which conceptually would be the result of the non-atomic assignment of integers.

Different programming languages ​​can freely define any semantics that they desire, it can be assumed that some of them will simply agree with any natural behavior in which the processor works (say, 32-bit int was atomic, 64-bit was not long), or they can do something smarter, and if the CPU itself does not provide atomic operations, then I do not see much alternative to the expected expectation, if they want to fake atomicity - for example. Java synchronized keyword.

Answer 2

If we are talking about atomic operations that are used by the synchronization mechanism (mutexes, semaphores, etc.), they should be supported by the OS on machines with one processor and hardware on several processors.

On one processor of a processor, a sequence of instructions can be made "atomic" in the sense that it cannot be interrupted in the middle (for example, a timer interrupt that gives a transition to another thread) if interrupts are disabled. This means that synchronization primitives can be written down quite simply after the CPU enters kernel mode and can access the interrupt control registers.

In a multi-core machine, this is more complicated. Then the instructions should be truly atomic in all CPUs. This requires that all processors, not just executing atomic instructions, hide the corresponding parts of their cache in RAM. This flushing makes synchronization so expensive on these architectures.

The instructions themselves take the form of “Bit test and set” in one operation. This is enough to implement a simple mutex. Even if two threads on different CPUs / cores perform a test and set the operation at the same time at the same address, only one will get the result that the bit has been canceled and is now set. This thread is the one that owns the mutex.

Answer 3

Depends on the atomic operation you are talking about. If you are talking about ISA level materials, I think the check and install instructions are included in some popular ISAs.