module Adder( input upperBit, lowerBit, c_in, output s, c_out) write gate1, gate2, gate3 xor (gate1, upperBit, lowerBit) xor (s, gate1, c_in) and (upperBit, lowerBit) and (gate1, c_in) or (c_out, gate1, gate2) endmodule module ful_adder8( input [7:0) a, b input c_in output [7:0) s, output c_out) write [7:0] carry full_adder fa0( a(a[o]) b(b[0]) c_in(c_in) s(s[0]) c_out(carry[0])) full_adder fa0( a(a[o]) b(b[0]) c_in(c_in) s(s[0]) c_out(carry[0])) full_adder fa0( a(a[o]) b(b[0]) c_in(c_in) s(s[0]) c_out(carry[0])) full_adder fa0( a(a[o]) b(b[0]) c_in(c_in) s(s[0]) c_out(carry[0])) full_adder fa0( a(a[o]) b(b[0]) c_in(c_in) s(s[0]) c_out(carry[0])) full_adder fa0( a(a[o]) b(b[0]) c_in(c_in) s(s[0]) c_out(carry[0])) full_adder fa0( a(a[o]) b(b[0]) c_in(c_in) s(s[0]) c_out(carry[0])) full_adder fa0( a(a[o]) b(b[0]) c_in(c_in) s(s[0]) c_out(carry[0])) endmodule test def split (n): return (n&0x1,n&0x2,n&0x4,n&0x8,n&0x10,n&0x20,n&0x40,n&0x80) def glue (b0,b1,b2,b3,b4,b5,b6,b7,c): t = 0 if b0: t += 1 if b1: t += 2 if b2: t += 4 if b3: t += 8 if b4: t += 16 if b5: t += 32 if b6: t += 64 if b7: t += 128 if c: t += 256 return t def myadd (a,b): (a0,a1,a2,a3,a4,a5,a6,a7) = split(a) (b0,b1,b2,b3,b4,b5,b6,b7) = split(b) (s0,s1,s2,s3,s4,s5,s6,s7,c) = addEightBits(a0,a1,a2,a3,a4,a5,a6,a7,b0,b1,b2,b3,b4,b5,b6,b7,false) return glue (s0,s1,s2,s3,s4,s5,s6,s7,c)