How to detect cold boot or warm boot on an ARM processor?

Question

I am looking for a way to determine if an ARM processor is loading from a cold boot file (i.e., starting up) compared to warm loading (i.e. reset without real power loss). In particular, I use the ARM968 core, it will determine the definition using C or assembly, and I will use the definition so that certain operations are performed only on initial power-up, and not on subsequent reset. In previous projects, I used external circuits (like FPGA) to detect various boot scripts, but in this case I am limited to the ARM core.

Answer 1

You can initialize the global variable in RAM with a value that is unlikely during cold boot, and check this at boot time.

Typically for microcontrollers, the reset logic of a particular chip provides a status register that indicates the reset source. I do not know if this exists for this larger kernel, and whether you can use it.

Answer 2

Check the documents for a specific chip ("ARM968" is not specific enough). There must be a register describing the reason for reset. For example. Here is what LPC23xx is:

Reset Source Identification Register (RSIR - 0xE01FC180) This register contains one bit for each source of Reset. Writing a 1 to any of these bits clears the corresponding read-side bit to 0. The interactions among the four sources are described below. Bit Symbol Description 0 POR Assertion of the POR signal sets this bit, and clears all of the other bits in this register. But if another Reset signal (eg, External Reset) remains asserted after the POR signal is negated, then its bit is set. This bit is not affected by any of the other sources of Reset. 1 EXTR Assertion of the RESET signal sets this bit. This bit is cleared by POR, but is not affected by WDT or BOD reset. 2 WDTR This bit is set when the Watchdog Timer times out and the WDTRESET bit in the Watchdog Mode Register is 1. It is cleared by any of the other sources of Reset. 3 BODR This bit is set when the 3.3 V power reaches a level below 2.6 V. If the VDD(DCDC)(3V3) voltage dips from 3.3 V to 2.5 V and backs up, the BODR bit will be set to 1. If the VDD(DCDC)(3V3) voltage dips from 3.3 V to 2.5 V and continues to decline to the level at which POR is asserted (nominally 1 V), the BODR bit is cleared. if the VDD(DCDC)(3V3) voltage rises continuously from below 1 V to a level above 2.6 V, the BODR will be set to 1. This bit is not affected by External Reset nor Watchdog Reset. Note: Only in case when a reset occurs and the POR = 0, the BODR bit indicates if the VDD(DCDC)(3V3) voltage was below 2.6 V or not. 

Answer 3

Most likely, it will be difficult, and perhaps you really do not mean only the core itself. The kernel should have received a reset, but the external memory (but possibly still inside the chip) did not. if the memory is based on drum, then it can be erased at boot. I do not know what overall size is suitable for all answers. both you and starblue have this, although you need to find some register somewhere that does not clear on reset, set this to something that "probably" will not happen by accident when you turn on the power. read it, then install. thinks fpga or pld, which control the reset logic at the board level (if any), are the best, since with power reset they are also reset, and on warm reset they are the one that called it and saved its state.

dig a TRM for your kernel or through the register specification for the chip and see if there are any registers whose state is reset undefined that you usually don’t use and do not damage the chip if you install this something and see what it activates , that’s where I start to search.