GNU Make Variables with scope limited to one Makefile

Question

I am trying to implement a non-recursive make build system in my current project. What I'm struggling with is areas of variables. The target specific variables do not meet my needs, as often the variables determine the goals, not the preconditions. What I need:

Makefile1:

SOMEVAR := original_value include Makefile2 $(warning $(SOMEVAR)) 

Makefile2:

 #some magic here to do what I want and make me happy SOMEVAR := included_value #and maybe here 

And the result that I want is "original_value".

Are there any strategies to make it real?

EDIT: The only solution I have made so far is to force and organize myself to put all inlcudes at the end of each specific Makefile and use the immediate variable assignment: =

Answer 1

One strategy is an old-fashioned solution to namespace conflicts when all you have is global variables: add a prefix to the variable names in the form of poor namespaces.

Makefile1:

 Makefile1_SOMEVAR := original_value include Makefile2 $(warning $(Makefile1_SOMEVAR)) 

Makefile2:

 # no magic needed Makefile2_SOMEVAR := included_value # rest of Makefile2 uses $(Makefile2_SOMEVAR) of course 

Hey presto, with the convention, as if each makefile has its own local variables (or at least its own variables in the namespace that do not interfere with any other makefiles).

Answer 2

use the override as follows:

Makefile1:

 override SOMEVAR := original_value include Makefile2 $(warning $(SOMEVAR)) 

Makefile2:

 #some magic here to do what I want and make me happy SOMEVAR := included_value #and maybe here