The address can be divided into the following parts:
[ tag | index | block or line offset | byte offset ]
The number of byte offset bits
0 for address memory, log 2 (bytes per word) for byte address memory
The number of bits to offset a block or row
log 2 (words per line)
The number of index bits
log 2 (CS), where CS is the number of cache sets.
- For a complete association, CS is 1. Since log 2 (1) is 0, there are no index bits.
- For Direct Mapped CS is CL, the number of cache lines, so the number of index bits is log 2 (CS) === log 2 (CL).
- For n-way associative CS = CL Γ· n: log 2 (CL Γ· n) index bits.
How many cached lines can you calculate by dividing the cache size by block size = S / B (assuming that both of them do not include the size for the tag and the actual bits).
Tag bits
Address length minus the number of bits used for offset (s) and index. The length of the addresses can be calculated using the size of the main memory, for example. any byte must be addressed if it is an address byte memory.
Source: http://babbage.cs.qc.edu/courses/cs343/cache_parameters.xhtml
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