Makefile with multiple executables

Question

I am trying to write a makefile that uses macros to create multiple executables from multiple files at once. I tried to find answers to the previously asked questions, but since I am quite new to programming in C, as well as working with gcc, I could not find the answer to my question.

Here is what I still have:

CC=gcc CFLAGS=-I. OBJ = ex1.c ex3.c EXECUTABLE = ex1 ex3 $(EXECUTABLE): $(OBJ) gcc -o $@ $^ $(CFLAGS) clean: rm -f $(EXECUTABLE) 

I need a string

 $(EXECUTABLE): $(OBJ) 

to create executable files ex1 and ex3 from files ex1.c ex3.c respectively.

Answer 1

In this particular case, when each executable has one source file with the extension .c , all you need is one line of Makefile:

 all: ex1 ex3 

Now the default built-in rules for make already work:

 $ make cc -O2 -pipe ex1.c -o ex1 cc -O2 -pipe ex3.c -o ex3 

Behind the make scene, the POSIXly built-in rule with one suffix is ​​used.

 .c: $(CC) $(CFLAGS) $(LDFLAGS) -o $@ $< 

Change the command to your liking with make CC=gcc CFLAGS=-O2 LDFLAGS=-s and the like.

General information of the day: in fact, if you want to name goals when calling make , you can use empty or even run without Makefile:

 $ make -f /dev/null CC=gcc CFLAGS=-O2 LDFLAGS=-s ex1 ex3 gcc -O2 -s ex1.c -o ex1 gcc -O2 -s ex3.c -o ex3 $ rm -f Makefile ex1 ex3 $ make CC=gcc CFLAGS=-O2 LDFLAGS=-s ex1 ex3 gcc -O2 -s ex1.c -o ex1 gcc -O2 -s ex3.c -o ex3 

Do the magic!

As a rule, do not reinvent the wheel (or rules), use the rules that already exist. It simplifies and makes life easier. It makes small and sexy makefiles to impress the ladies :-)

Answer 2

Some suggestions (assuming you are using GNU make , not something else)

First run make -p once, you will realize that you know the built-in rules of make . Take a look in particular at COMPILE.c and LINK.c

Then i suggest

  CFLAGS= -g -Wall -I. 

^{(because you really want -g to debug and -Wall get most warnings)}

And you probably don't need

 $(EXECUTABLE): $(OBJ) gcc -o $@ $^ $(CFLAGS) 

However, I suggest adding before most other rules

 .PHONY: all clean all: $(EXECUTABLES) 

Actually, I would encode your Makefile (for GNU make !), As follows

 # file Makefile CC= gcc RM= rm -vf CFLAGS= -Wall -g CPPFLAGS= -I. SRCFILES= ex1.c ex2.c ## or perhaps $(wildcard *.c) OBJFILES= $(patsubst %.c, %.o, $(SRCFILES)) PROGFILES= $(patsubst %.c, %, $(SRCFILES)) .PHONY: all clean all: $(PROGFILES) clean: $(RM) $(OBJFILES) $(PROGFILES) *~ ## eof Makefile 

Remember that tab is a significant character in Makefile -s (part of the rules action). In this answer, lines starting with four spaces should at least begin with a tab character.

Once everything is debugged, run make clean to clean everything, and then make -j CFLAGS=-O2 all to compile everything with optimization.

Finally, I recommend using remake and running remake -x to debug the Makefile -s complex

Of course, I assume that your directory has only single-file programs.

By the way, there are other software developers. You might consider omake

^{Remember to use a version control system like git for your source files. It's time to also learn such a tool.}

Answer 3

You are close, but you need a template rule:

 $(EXECUTABLE): % : %.c 

And then the default rule to make it like:

 all: $(EXECUTABLE) 

Answer 4

The following answer includes several executables, such as initiate, process1, process2, ..., process4.

 LOCAL_INCLUDE=./ all: clean process_first process_second init process_first: gcc -g -o process1 -I$(LOCAL_INCLUDE) process1.c -lzmq -L. -L./. gcc -g -o process2 -I$(LOCAL_INCLUDE) process2.c -lzmq -L. -L./. process_second: gcc -g -o process3 -I$(LOCAL_INCLUDE) process3.c -lzmq -L. -L./. gcc -g -o process4 -I$(LOCAL_INCLUDE) process4.c -lzmq -L. -L./. init: gcc -g -o initiate -I$(LOCAL_INCLUDE) initiate.c -lzmq -lconfig -lpthread -L. -L./. -ldl -lrt clean: rm -rf init_manager.o init_manager rm -rf process1 process2 process3 process4 

NOTE. Good practice is to clean and touch all executable files before doing them again.