Comparing long std_logic_vector with zeros

Question

In simulation, this works fine. This is the best way to check for zeros for synthesized code. What will be the resources?

signal vector_slv : std_logic_vector(2048 downto 0); ... if (vector_slv = (vector_slv'range => '0')) then -- do something... 

Is there any other optimal way to implement this solution, given the h / w mapping (with optimal use of resources).

I would be more interested in understanding the resources used.

Answer 1

There is no way that makes more or less sense for synthesis. Write the code that best expresses your intention.

If you are comparing a vector for all zeros, everyone should give the same results or you must file a serious error regarding the tool!

 signal vector_slv : std_logic_vector(2048 downto 0); constant zeros : std_logic_vector(vector_slv'range) := (others => '0'); ... if vector_slv = (vector_slv'range => '0') then -- do something... if vector_slv = zeros then -- do something... if unsigned(vector_slv) = to_unsigned(0, vector_slv'length) then -- do something... 

and valid for shorter vectors that fit into an integer:

 if intvar = 0 then 

will be exactly the same as any 32-bit vector comparison.

<sub> (BTW, notice that there is no need for parentheses around the if -VHDL condition is not C :) Sub>

Answer 2

If the range is available, as in your code example, then the solution offer looks great, and I expect the synthesis tools to handle such constructs.

If the range is not available, a comparison with zero can be done like this:

 library ieee; use ieee.numeric_std.all; ... if unsigned( {std_logic_vector expression of any length} ) = 0 then -- do something... 

I would expect the synthesis tools to handle this the same way as for comparing with (vector_slv'range => '0') .

Answer 3

As far as synthesis is concerned, yes, such simple constructions are usually well optimized by the instrument. The exact layout of the equipment, of course, depends on your goal (FPGA, ASIC, ...).

My suggestion is to take a look at the result of the synthesis (for example, Altera FPGA technology map viewer). If synthesis collapses it, you can manually convert it to a binary tree of comparisons with zero, taking into account the technological primitives that you have. It can be a lot more complicated than it sounds, especially for the FPGA (there is more than LUT to play with it), and not necessarily with a decent tool.

Answer 4

You can also separate the predicate and assignment by doing this:

 signal is_zero : boolean; signal vector_slv : std_logic_vector(2048 downto 0); ... process(clk) begin if rising_edge(clk) then is_zero <= vector_slv = (vector_slv'range => '0'); if is_zero then ... end if; end if; end process; 

This should greatly improve your timeline. Note that the is_zero predicate is now a delayed version of your original comparison!