I2C is quite involved, supporting several masters on the bus. This causes significant overhead in the bus protocol, ACK for each byte, and deliberate delays for arbitration of bus access. The maximum bus frequency of 100 kHz in the original specification is also set, 400 kHz, today, additional high-speed modes of 10 kHz and 3.4 MHz are high-frequency, the 2012 specification defines an ultrafast 5 MHz mode.
SPI is much simpler, a single master without a bus protocol is beyond the scope of the chip choice and does not set the maximum bus frequency. If the distances are short, you can go as fast as you dare. Pretty quickly on the interconnect between the chips, located at a distance of less than an inch.
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