Assign one bit from STD_LOGIC_VECTOR to STD_LOGIC

Question

I seem to have done this many times, but for some reason today he just doesn't want to work.

I would like to assign an MSB 16 bit vector to a single bit variable.

Din : in STD_LOGIC_VECTOR (15 downto 0); ... signal signBit : std_logic; begin signBit <= Din(15 downto 15); 

Indicated error:

 Type of signBit is incompatible with type of Din. 

Yes, I get this, vectors do not play well with std_logic, but it is 1-bit clearly marked (15 downto 15)

Answer 1

 Din(15 downto 15); 

- std_logic_vector, 1 bit long

 Din(15); 

- one of the std_logic_vector elements, i.e. std_logic.