If memory is addressed by byte
This statement simply states that the main memory is the address of the byte addressed, i.e. architectures to which data can be accessed 8 bits at a time, regardless of the data bus width and address.
This does not affect the number of bits the tag has.
Decision:
4-way associative association
Total cache = 4096 bytes
Block size (cache line) = 128 bytes
Number of cache lines = 4096/128 = 32 lines
The number of sets in the cache = 32/4 = 8 sets
ββββββββββββββββββββββββββββββ β 16 bit address β β βββββββββββ€βββββββββ€βββββββββ£ β tag bit? β 3 bits β 7 bits β ββββββββββββ§βββββββββ§βββββββββ
Word offset = log 2 8 = 3 bits
Set offset = log 2 128 = 7 bits
Answer:
Label bit = 16 - (3 + 7) = 6 bits
ββββββββββββββββββββββββββββ β 16 bit address β β βββββββββ€βββββββββ€βββββββββ£ β 6 bits β 3 bits β 7 bits β ββββββββββ§βββββββββ§βββββββββ
Alwyn mathew
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