How to use clock strobe in RTL?

Question

I set the clock with latch and logic in my design. I do not have much experience in synthesis, placement, and routing. What is the correct way to do clock synchronization in RTL?

Example 1:

always_comb begin gated_clk = clk & latch_update_en; end always_latch begin if(gated_clk) begin latch_data <= new_data; end end 

Example 2: I came across RTL examples while doing some research on good practices in RTL sync strings. In this example, the above code is implemented as follows:

 clock_gator cg_cell (.clk(clk), .en(latch_update_en), .scan_en(scan_en_in), .gated_clk(gated_clk)); always_latch begin if(gated_clk) begin latch_data <= new_data; end end 

What is the purpose of using a custom sync cell? Is the process complicated in the synthesis if clk is directly "and" in the always_comb block with a different permission signal? I get the feeling that using a special gating sync cell is the standard approach to the generated synchronized clock. I am trying to understand why this is so.

Answer 1

What is the correct way to implement clock gating in RTL?

The clock strobe signal should only be switched when the latch is closed, otherwise there is the possibility of failures and problems with metastability. For an active high latch, the strobe signal must switch to the falling edge of the clock. Edge increase for active low latches.

Typically, you would have to have an edge-sensitive latch_update_en flop to prevent interference on the gate signal.

 always_ff @(negedge clk) latch_update_en <= next_latch_update_en; always_comb gated_clk = (* clock_gating = "clk" *) clk & latch_update_en; always_latch if(gated_clk) latch_data <= new_data; 

Reminder: if you have a latch only deign: front trigger shutters are only master / slave latches

 always_latch if (clk) sync_latch_update_en <= next_latch_update_en; always_latch if (!clk) latch_update_en <= sync_latch_update_en; 

Does the tool have a difficult time in synthesis, if clk directly "and" - in the always_comb block with a different permission signal?

Most synthesis has problems with direct I-synchronization. It is not always intuitive how to use gating. A synthesizer often has many AND logic elements in the library to select, each of which has different slope, skew, and load values, which is very important for input combinations. Although functionally the same, A & B will get different time results, then B & A

Initiating an explicit cell from a synthesizer library narrows the possibilities for knowing and predicting behavior. The predefined clock strobe cell also has the attributes used by the synthesizer. Attributes include synchronization information for balancing the clock tree (placing a buffer in the design to manage loads and parasites).

Some synthesizers support setting tag attributes in RTL (ex: // synthesis attributes or (* attributes *) ) instead of having to explicitly create a cell instance. There is no standard on how to do this; refer to the user manual.

What is the purpose of using a custom clock strobe cell?

A user cell is a specific cell in the synthesis library with information about time synchronization, load balancing, and other attributes. Using this information, the synthesizer knows where and how to add or calibrate the buffer delay in the clock tree. This ensures that the fleet with closed gates does not see the front of the clock before the flop.

  _____ _____ IN -------------|DQ|-----|DQ|--- OUT | | | | |\ |\ | | | | +-| >| >---|> | +-|> | | |/ |/ |_____| | |_____| | ___ | CLK -+-| \ | | & )-------------+ BALANCED CLOCK : correct data sampled GATE --|___/ 

Without an indication, a closed flop may receive a delayed clock. Beveling will result in incorrect data being selected.

  _____ _____ IN -------------|DQ|-----|DQ|--- OUT | | | | | | | | +----------|> | +-|> | | |_____| | |_____| | ___ | CLK -+-| \ |\ |\ | | & )---| >| >----+ UNBALANCED CLOCK : wrong data sampled GATE --|___/ |/ |/