Didn't get the right answer here .
If it is a DMA controller, then what is the difference between DMA and interrupt based transmission
This question has not received good IMO answers, because the question is erroneously worded.
In fact, I do not understand his description of "interruption" because it is pointless, and it is not because I lack knowledge and experience in this area. DMA is not an alternative to interrupts.
Instead, they are orthogonal concepts, and both concepts are commonly used together .
An alternative to DMA is programmed I / O as well as PIO.
An alternative to interrupts is polling.
DMA transmission almost always uses completion interrupt (from the DMA controller) to notify the CPU of the completion of the buffer transfer.
PIO often uses an interrupt (from the device) to initiate the transmission of each byte / word. This helps reduce processor intensity in PIO. The interrogated PIO transmission would otherwise completely consume CPU resources.
But refer to “PIO with interrupts” because simply “interrupts” are inaccurate and misleading.
Interrupt-based UART IO enables data transfer without CPU intervention. Now the question is, if not the CPU that controls this?
You did not specify the source of the interrupt; therefore your question is ambiguous.
If “interrupt-based” is supposed to refer to “PIO with interrupt from UART”, then the question does not make sense, since it is the processor that controls the transfer.
If it is assumed that “interrupt-based” refers to the transfer of DMA with interrupts from the DMA controller, you use these terms in a context that was not previously used in your or related matters.
To read UART:
In a DMA transmission, each byte is read from the UART (when the UART signals that data is available) and written to the memory by the DMA controller. To complete this task, you must configure the DMA controller. As long as the DMA controller controls this transfer, the CPU will execute other (supposedly unrelated) instructions (for example, for another process).
In PIO transmission, the processor monitors all the time, following instructions for reading from the device and writing to memory.
This is a DMA controller or some external master that takes control of the memory bus from the CPU.
The memory bus is supported by the memory controller. No other device takes control of the memory bus.
For a real read or write to the memory, the DMA controller requests access to the memory during DMA transmission.
Note that there are privileged devices, such as a bus master or coprocessor / GPU, that may also request memory access.
But the CPU is usually given the highest priority for memory access.